Superconductor integrated circuit fabrication technology

Proceedings of the IEEE

Volumn 92, Issue 10, 2004, Pages 1517-1533

  Abelson, Lynn A ^a   Kerber, George L ^a,b  

^a NORTHROP GRUMMAN CORPORATION   (United States)

^b NONE

Author keywords

100 GHz digital logic; Anodization; Critical current; Flip flop; Foundry; Interlevel dielectric; Josephson junction; Niobium; Niobium nitride; Photolithography; Planarization; Quantum computing; Qubit; Rapid single flux quantum (RSFQ); Reactive ion etch; Resistor

Indexed keywords

ANODIC OXIDATION; CRITICAL CURRENTS; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP FLOP CIRCUITS; FOUNDRIES; INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS; NICKEL; NIOBIUM; NIOBIUM COMPOUNDS; PHOTOLITHOGRAPHY; REACTIVE ION ETCHING; SILICA;

100-GHZ DIGITAL LOGIC; INTERLEVEL DIELECTRIC; JOSEPHSON JUNCTION; NIOBIUM NITRIDE; PLANARIZATION; QUANTUM COMPUTING; SIO2; SUPERCONDUCTOR INTEGRATED CIRCUIT; TRILAYER;

SUPERCONDUCTING DEVICES;

EID: 21244448653     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2004.833652     Document Type: Conference Paper

References (105)

1. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems," IEEE Trans. Appi. Superconduct., vol. 1, pp. 3-28, Mar. 1991.
2. W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, and K. K. Likharev, "Rapid single flux quantum T-flip flop operating up to 770 GHz," IEEE Trans. Appl. Superconduct., vol. 9, pp. 3212-3215, June 1999.
3. K. K. Likharev, "RSFQ: The fastest digital technology," in Proc. 5th Eur. Workshop Low Temperature Electronics 2002. p. 155.
4. T. Sterling, "How to build a hypercomputer," Sci. Amer., pp. 38-45, July 2001.
5. T. Sterling, G. Gao, K. K. Likharev, P. M. Kogge, and M. J. MacDonald, "Steps to petaflops computing: A hybrid technology multithreaded architecture," in Proc. IEEE Aerospace Conf. 1997, vol. 2, pp. 41-75.
6. K. B. Theobald, G. R. Gao, and T. L. Sterling, "Superconducting processors for HTMT: Issues and challenges." in Proc. 7th Symp. Frontiers of Massively Parallel Computation 1999, pp. 260-267.
7. K. K. Likharev, "Superconductor devices for ultrafast computing." in Applications of Superconductivity, H. Weinstock. Ed. Dordrecht, The Netherlands: Kluwer, 1999.
8. International Technology Roadmap for Semiconductors: Emerging research devices (2003). [Online]. Available: http://public.itrs.net/Files/2003ITRS/ ERD2003.pdf
9. M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai, and S. Yorozu, "A single-flux-quantum logic prototype microprocessor," in Dig. Tech. Papers 2003 IEEE Int. Solid-State Circuits Conf., pp. 1-3.
10. J. Spargo, Q. Herr, and L. Abelson, "High speed digital devices, circuits, and applications in the U.S.," in Extended Abstracts 8th Int. Superconductivity Electronics Conf., 2001, pp. 101-102.
11. P. Bunyk, K. Likharev. and D. Zinoviev, "RSFQ technology: Physics and devices," Int. J. High Speed Electron. Syst., vol. 11, pp. 257-305, 2001.
12. Y. Makhlin, G. Schön, and A. Shnirman, "Quantum-state engineering with Josephson-junction devices." Rev. Mod. Phys., vol. 73, pp. 357-400, Apr. 2001.
13. V. K. Semenov and D. V. Averin, "SFQ control circuits for Josephson junction qubits." IEEE Trans. Appl. Superconduct., vol. 13, pp. 960-965, June 2003.
14. M. F. Bocko, A. M. Herr, and M. J. Feldman, "Prospects for quantum coherent computation using superconducting electronics," IEEE Trans. Appl. Superconduct., vol. 7, pp. 3638-3641, June 1997.
15. A. W. Kleinsasser, "High performance Nb Josephson devices for petaflops computing," IEEE Trans. Appl. Superconduct., vol. 11, pp. 1043-1049, Mar. 2001.
16. L. A. Abelson, Q. P. Herr, G. L. Kerber, M. Leung, and T. S. Tighe, "Manufacturability of superconductor electronics for a petaflops-scale computer," IEEE Trans. Appl. Superconduct., vol. 9, pp. 3202-3207, June 1999.
17. A. Silver, A. Kleinsasser, G. Kerber, Q. Herr, M. Dorojevets, P. Bunyk, and L. Abelson, "Development of superconductor electronics technology for high end computing," Supercond. Sci. Technol., vol. 16, pp. 1368-1374, Oct. 2003.
18. G. L. Kerber, L. A. Abelson, K. Edwards, R. Hu, M. W. Johnson, M. L. Leung, and J. Luine, "Fabrication of high current density Nb integrated circuits using a self-aligned junction anodization process," IEEE Trans. Appl. Superconduct., vol. 13, pp. 82-86, June 2003.
19. Q. P. Herr, M. S. Wire, and A. D. Smith, "High speed data link between digital superconductor chips," Appl. Phys. Lett., vol. 80, pp. 3210-3212, Apr. 2002.
20. 2 dielectric films," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2303-2309, June 1995.
21. x /Nb process," IEEE Trans. Appl. Superconduct., vol.9, pp. 3271-3274, June 1999.
22. 3-Al/Nb process development for the fabrication of fast-switching circuits in RSFQ logic." in Proc. 2nd Eur. Conf. Applied Superconductivity (EUCAS'95), vol. 2, pp. 1709-1712.
23. D. Balashov, M. I. Khabipov, F.-Im. Buchholz, W. Kessel, and J. Niemeyer, "SINIS fabrication process for realizing integrated circuits in RSFQ impulse logic." Supercond. Sci. Technol., vol. 12, pp. 864-867, 1999.
24. M. I. Khabipov, D. Balashov, F-Im. Buchholz, W. Kessel, and J. Niemeyer, "RSFQ circuitry realized in a SINIS technology process." IEEE Trans. Appl. Superconduct., vol. 9, pp. 4682-4687, Dec. 1999.
25. x-Al/Nb tunnel junctions with high critical current densities," IEEE Trans. Appl. Superconduct., vol. 11, pp. 365-368, Mar. 2001.
26. M. Maezawa, M. Suzuki, and A. Shoji, "Design and operation of a rapid single flux quantum demultiplexer," Supercond. Sci. Technol., vol. 15, pp. 1744-1746, 2002.
27. H. Yamamori, M. Itoh, H. Sasaki, S. P. Benz, and P. D. Dresselhaus, "All-NbN digital-to-analog converters for a programmable voltage standard," Supercond. Sci. Technol., vol. 14, p. 1048, Dec. 2001.
28. HYPRES design rules. HYPRES, Elmsford, NY. [Online]. Available: http://www.hypres.com
29. S. Topylgo, private communication, Nov. 2003.
30. J. C. Villegier, M. Salez, F. Miletto-Granozio, and A. Karpov, "Processing and characterization of high Jc NbN superconducting tunnel junctions for THz analog circuits and RSFQ," IEEE Trans. Appl. Superconduct., vol. 9, pp. 3216-3219, June 1999.
31. G. L. Kerber, L. A. Abelson, R. N. Elmadjian, and E. G. Ladizinsky, "Characteristics of junctions and resistors fabrication using an all-NbN superconductor integrated circuit foundry process," IEEE Trans. Appl. Superconduct., vol. 9, pp. 3267-3270, June 1999.
32. x/Nb Josephson junctions." IEEE Trans. Appl. Superconduct., vol. 13, pp. 103-106, June 2003.
33. S. Tahara, S. Yorozu, Y. Kameda, Y. Hashimoto, H. Numata, T. Satoh, W. Hattori, and M. Hidaka, "Superconducting digital electronics." IEEE Trans. Appl. Superconduct., vol. 11, pp. 463-468, Mar. 2001.
34. L. Fritzsch. H. Elsner, M. Schubert, and H.-G. Meyer, "SNS and SIS Josephson junctions with dimensions down to the sub-micron region prepared by a unified technology," Supercond. Sci. Technol., vol. 12, pp. 880-882, 1999.
35. S. P. Benz, "Superconductor-normal-superconductor junctions for programmable voltage standards," Appl. Phys. Lett., vol. 67, pp. 2714-2716, Oct. 1995.
36. R. Lochschmied, R. Herwig, M. Neuhaus, and W. Jutzi, "A low power 12 bit flux shuttle shift register with Nb technology," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2983-2986, June 1997.
37. H. Terai and Z. Wang, "9 K operation of RSFQ logic cells fabricated by NbN integrated circuit technology," IEEE Trans. Appl. Superconduct., vol 11, pp. 525-528, Mar. 2001.
38. O. Kieler, R. Behr, F. Müller, H. Schulze, J. Kohlmann, and J. Niemeyer, "Improved 1 V programmable Josephson voltage standard using SINIS junctions," Physica C, vol. 372-376, pp. 309-311, 2002.
39. J. K. Freericks, B. K. Nikolic, and P. Miller, "Superconductor- correlated metal-superconductor Josephson junctions: An optimized class for high speed digital electronics," IEEE Trans. Appl. Superconduct., vol. 13, pp. 1089-1092, June 2003.
40. I. P. Nevirkovets, S. E. Shafranjuk, J. B. Ketterson, and E. M. Rudenko, "Properties of high-jc SINIS junctions," IEEE Trans. Appl. Superconduct., vol. 13, pp. 1085-1088, June 2003.
41. L. Abelson, "Superconductive electronics process technologies," in Extended Abstracts 6th Int. Superconductivity Electronics Conf., June 1997, pp. 1-4.
42. x/Nb integrated circuits using low temperature and low stress ECR PECVD silicon oxide films." IEEE Trans. Appl. Superconduct., vol. 9, pp. 3208-3211, June 1999.
43. A. Shoji, M. Aoyagi, S. Kosaka, and F. Shinoki, "Temperature- dependent properties of niobium nitride Josephson tunnel junctions," IEEE Trans. Magn., vol. 23, pp. 1464-1471, Mar. 1987.
44. M. Radparvar, L. S. Yu-Jahnes, and R. T. Hunt, "All niobium nitride Josephson tunnel junctions with thermally oxidized magnesium barrier," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2050-2053, Mar. 1993.
45. S. Kubo, M. Asahi, M. Hikita, and M. Igarashi, "Magnetic penetraiion depths in superconducting NbN films prepared by reactive dc magnetron sputtering." Appl. Phys. Lett., vol. 44, pp. 258-260, Jan. 15, 1984.
46. S. L. Thomasson, A. W. Moopenn, R. Elmadjian, J. M. Murduck, J. W. Spargo, L. A. Abelson, and H. W. Chan, "All refractory NbN integrated circuit process," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2058-2061, Mar. 1993.
47. B. Bumble, H. G. LeDuc, J. A. Stem, and K. G. Megerian, "Fabrication of Nb/Al-Nx/NbTiN junctions for SIS mixer applications." IEEE Trans. Appl. Superconduct., vol 11, pp. 76-79, Mar. 2001.
48. M. Gurvitch, W. A. Washington, and H. A. Huggins, "High quality refractory Josephson tunnel junctions utilizing thin aluminum layers," Appl. Phys. Lett., vol. 42, pp. 472-474, Mar. 1983.
49. Y. Tarutani, M. Hirano, and U. Kawabe, "Niobium-based integrated circuit technologies," in Proc. IEEE, vol. 77, Aug. 1989, pp. 1164-1176.
50. x-Al/Nb Josephson junctions. I. Sputtered Nb films for junction electrodes," IEEE Trans. Appl. Superconduct., vol. 2, pp. 1-14, Mar. 1992.
51. x-Al/Nb Josephson junctions. II. Deposition of thin Al layers on Nb films." IEEE Trans. Appl. Superconduct., vol. 2, pp. 84-94, June 1992.
52. x tunneling barriers," IEEE Trans. Appl. Superconduct., vol. 2, pp. 222-227, Dec. 1992.
53. x/Nb Josephson junctions," IEEE Trans. Magn., vol. 25, pp. 1119-1122, Mar. 1989.
54. K. Tsukada, J. Kawai, G. Uehara, and H. Kado, "Relationship of Nb surface morphology and Al coverage to the intrinsic stress of magnetron-sputtered Nb films," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2944-2946, Mar. 1993.
55. P. A. A. Booi, C. A. Livingston, and S. P. Benz, "Intrinsic stress in DC sputtered niobium," IEEE Trans. Appl. Superconduct., vol. 3, pp. 3029-3031, June 1993.
56. R. S. Amos, P. E. Breyer, H. H. Huang, and A. W. Lichtenberger, "Stress and source conditions of DC magnetron sputtered Nb films," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2326-2329, June 1995.
57. K. Kuroda and M. Yuda, "Niobium-stress influence on Nb/Al-oxide/Nb Josephson junctions," J. Appl. Phys., vol. 63, pp. 2352-2357, Apr. 1, 1988.
58. x-Nb tunnel junctions," IEEE Trans. Appl. Superconduct., vol. 5, pp. 26-30, Mar. 1995.
59. 2 Nb integrated circuit process," IEEE Trans. Appl. Superconduct., vol. 11, pp. 1061-1065, Mar. 2001.
60. x/Nb Josephson junctions using ECR plasma etching technique," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2644-2648, June 1997.
61. H. Kroger, L. N. Smith, and D. W. Jillie, "Selective niobium anodization process for fabricating Josephson junctions," Appl. Phys. Lett., vol. 39, pp. 280-282, Aug. 1, 1981.
62. x/Nb Josephson junctions." Appl. Phys. Lett., vol. 48-3212, pp. 254-256. Jan. 20, 1986.
63. L. P. S. Lee, E. R. Arambula, G. Hanaya, C. Dang, R. Sandell, and H. Chan, "RHEA (resist-hardened etch and anodization) process for fine-geometry Josephson junction fabrication," IEEE Trans. Magn., vol. 27, pp. 3133-3136, Mar. 1991.
64. x/Nb tunnel junctions with high critical current densities," IEEE Trans. Appl. Superconduct., vol. 11, pp. 365-368, Mar. 2001.
65. AZ-300T photoresist stripper and AZ 3318D photoresist. Clariant Corp., Somerville, NJ. [Online]. Available: http://azwebsale@clariant.com
66. 2 topological design rules, JJ110E, Rev. 2.2." NGST, Redondo Beach, CA.
67. L. Abelson, K. Daly, N. Martinez, and A. D. Smith, "LTS Josephson critical current densities for LSI applications," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2727-2730, June 1995.
68. S. Hasuo, "High-speed Josephson integrated circuit technology." IEEE Trans. Magn., vol. 25, pp. 740-749, Mar. 1989.
69. G. L. Kerber, L. A. Abelson, R. N. Elmadjian, G. Hanaya, and E. G. Ladizinsky, "An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances," IEEE Trans. Appl. Superconduct., vol. 7, pp. 2638-2643, June 1997.
70. H. Numata and S. Tahara, "Fabrication technology for Nb integrated circuits," IEICE Trans. Electron., vol. E84-C, pp. 2-8, Jan. 2001.
71. J. S. Logan, F. S. Maddocks, and P. D. Davidse, "Metal edge coverage and control of charge accumulation in rf sputtered insulators," IBM J. Res. Develop., vol. 14, pp. 182-191, Mar. 1970.
72. J. P. Ducommum, M. Cantagrel, and M. Moulin, "Evolution of well-defined surface contour submitted to ion bombardment: Computer simulation and experimental investigation," J. Mater. Sci., vol. 10, pp. 52-62, 1975.
73. 2," J. Vac. Technol., vol. 15, pp. 1105-1112, May-June 1978.
74. C. H. Ting and A. R. Neureuther, "Applications of profile simulation for thin film deposition and etching processes," Solid State Technol., vol. 25, pp. 115-123, Feb. 1982.
75. A. Mumtaz, I. Drapkin, and R. Mathew, "Radio frequency magnetron sputtering of radio frequency biased quartz on a scanning pallet," J. Vac. Sci. Technol. A, vol. 2, pp. 237-240. Apr-June 1984.
76. J. S. Logan, "Control of RF sputtered film properties through substrate tuning," IBM J. Res. Develop., vol. 14, pp. 172-175, Mar. 1970.
77. 2 during growth and its relation to film quality," IBM J. Res. Develop., vol. 14, pp. 176-181, Mar. 1970.
78. S. Hasuo and T. Imamura, "Digital logic circuits." Proc. IEEE, vol. 77, pp. 1177-1193, Aug. 1989.
79. S. Nagasawa, H. Tsuge, and Y. Wada, "Planarization technology for Josephson integrated circuits," IEEE Electron Device Lett., vol. 9, pp. 414-416, Aug. 1988.
80. I. Ishida, S. Tahara, M. Hidaka, S. Nagasawa, S. Tuschida, and Y. Wada, "A fabrication process for a 580 ps 4 kbit Josephson nondestructive read-out RAM," IEEE Trans. Magn., vol. 27, pp. 3113-3116, Mar. 1991.
81. 2 dielectric," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2201-2203, Mar. 1993.
82. K. Kikuchi, S. Segawa, E.-S. Jung, H. Nakagawa, K. Tokoro, H. Itatani, and M. Aoyagi, "New fabrication process for Josephson tunnel junctions using photosensitive polyimide insulation layer for superconducting integrated circuits," IEEE Trans. Appl. Superconduct., vol. 13, pp. 119-122, June 2003.
83. H. Numata, S. Nagasawa, M. Tanaka, and S. Tahara, "Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization," IEEE Trans. Appl. Superconduct., vol. 9, pp. 3198-3201, June 1999.
84. x-Nb Josephson process for 125 mm wafers developed in partnership with Si technology," Appl. Phys. Lett., vol. 59, pp. 2609-2611, Nov. 1991.
85. x/Nb Josephson junctions using chemical mechanical polishing," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2731-2734, June 1995.
86. J. M. Murduck, A. Kirschenbaum, A. Mayer, V. Morales, and C. Lavoie, "High-performance Nb integrated circuit process fabrication," IEEE Trans. Appl. Superconduct., vol. 13, pp. 87-90, June 2003.
87. C. J. Kircher and H. H. Zappe, "Process for fabricating above and below ground plane wiring on one side of a supporting substrate and the resulting circuit configuration," U.S. Patent 4075 756, Feb. 1978.
88. D. C. Montgomery, Introduction to Statistical Quality Control, 2nd ed. New York: Wiley, 1991.
89. A. A. Joseph, S. Heuvelmans, G. J. Gerritsma, and H. G. Kerkhoff, "The detection of defects in a niobium tri-layer process," IEEE Trans. Appl. Superconduct., vol. 13, pp. 95-98. June 2003.
90. L. A. Abelson, S. L. Thomasson, J. M. Murduck, R. Elmadjian, G. Akerling, R. Kono, and H. W. Chan, "A superconductive integrated circuit foundry," IEEE Trans. Appl. Superconduct., vol. 3, no. 1, pp. 2043-2049, Mar. 1993.
91. V. K. Semenov, Yu. A. Polyakov, and W. Chao, "Extraction of impacts of fabrication spread and thermal noise on operation of superconducting digital circuits," IEEE Trans. Appl. Superconduct., vol. 9, pp. 4030-4033, June 1999.
92. W. Y. Fowles and C. M. Creveling, Engineering Methods for Robust Product Design Using Taguchi Methods in Technology and Product Development. Reading, MA: Addison-Wesley, 1995.
93. G. Box, W. Hunter, and J. Hunter, Statistics for Experiments. New York: Wiley, 1978.
94. J. M. Murduck, J. DiMond, C. Dang, and H. Chan, "Niobium nitride Josephson process development," IEEE Trans. Appl. Superconduct., vol. 3, pp. 2211-2214, Mar. 1993.
95. A. V. Ferris-Prabhu, Introduction to Semiconductor Device Yield Modeling. Norwood, MA: Artech House, 1992.
96. D. L. Miller, J. X. Przybysz, and J. H. Kang, "Margins and yields of SFQ circuits in HTS materials." IEEE Trans. Appl. Supercfmduct., vol. 3, pp. 2728-2731, Mar. 1993.
97. C. A. Hamilton and K. C. Gilbert, "Margins and yield in single flux quantum logic," IEEE Trans. Appl. Superconduct., vol. 1, pp. 157-163, Dec. 1991.
98. D. J. Durand, L. A. Abelson, L. R. Eaton, M. Leung, A. Moopenn, J. M. Murduck, and J. Spargo, "Ten kelvin NbN integrated digital circuits," in Extended Abstracts 4th Int. Superconductivity Electronics Conf., 1993, pp. 209-210.
99. S. Tahara, S. Nagasawa, H. Numata, Y. Hashimoto, S. Yorozu, and H. Matsuoka, "Josephson digital LSI technology," in Extended Abstracts 5th int. Superconductivity Electronics Conf., 1995, pp. 23-25.
100. W. Chen, A. V. Rylyakiv, V. Patel, J. E. Lukens, and K. K. Likharev, "Superconductor digital frequency divider operating up to 750 GHz," Appl. Phys. Lett., vol. 73, pp. 2817-2819, Nov. 1998.
101. D. K. Brock, A. M. Kadin, A. F. Kirichenko, O. A. Mukhanov, S. Sawana, J. A. Vivalda, W. Chen, and J. E. Lukens, "Retargetting RSFQ cells to a submicron fabrication process," IEEE Trans. Appl. Superconduct., vol. 11, pp. 369-372, Mar. 2001.
102. R. Pullela, D. Mensa, B. Argarwal, Q. Lee, J. Guthrie, and M. J. W. Rodwell, "47 GHz static frequency divider in ultrafast transferred- substrate heterojunction bipolar transistor technology," presented at the Conf. InP and Related Materials, Tsukuba, Japan, 1998.
103. M. W. Johnson, B. J. Dalrymple, and D. J. Durand, "Wide bandwidth oscillator/counter A/D converters." IEEE Trans. Appl. Superconduct., vol. 11, pp. 607-611, Mar. 2001.
104. A. Kleinsasser, E-beam lithography tool. Jet Propulsion Lab, Pasadena, CA. [Online]. Available: http://Alan.W.Kleinsasser@jpl.nasa.gov
105. P. Bunyk, "RSFQ random logic gate density scaling for the next-generation Josephson junction technology," IEEE Trans. Appl. Superconduct., vol. 13, pp. 496-497, 2003.