Fabrication technology for high-density josephson integrated circuits using mechanical polishing planarization

IEEE Transactions on Applied Superconductivity

Volumn 9, Issue 2 PART 3, 1999, Pages 3198-3201

  Numata, Hideaki ^a   Nagasawa, Shuichi ^a   Tanaka, Michi ^a   Tahara, Shuichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; INTEGRATED CIRCUIT MANUFACTURE; POLISHING; SCANNING ELECTRON MICROSCOPY; SILICA; SILICON WAFERS; SPATIAL VARIABLES CONTROL; SPUTTERING;

HIGH DENSITY JOSEPHSON INTEGRATED CIRCUITS; INTERLAYER INSULATION; MECHANICAL POLISHING PLANARIZATION;

JOSEPHSON JUNCTION DEVICES;

EID: 0032655579     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.783709     Document Type: Article

References (7)

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