A 12b 80MSps pipelined ADC core with 190mW consumption from 3V in 0.18μm digital CMOS

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 467-470

  Loloee, Arash ^a   Zanchi, Alfio ^a   Jin, Huawen ^a   Shehata, Shereef ^a   Bartolome, Eduardo ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CORES; CMOS PROCESSS; DIGITAL CMOS; DSP CORE; FIGURE OF MERITS; PIPELINED ADCS;

CMOS INTEGRATED CIRCUITS;

EID: 0348128237     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Y.-I. Park et al., "A 10b 100Msample/s CMOS pipelined ADC with 1.8V power supply", Proceedings ISSCC 2001, vol. 44, pp. 130-131.
2. A. Abo and P. Gray, "A 1.5V 10b 14.3 MSps CMOS pipeline analog-to-digital converter", IEEE Journal of Solid-State Circuits, vol. 34, May 1999, pp. 599-606.
3. K. Bult and G.J.G.M. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain'", IEEE Journal of Solid-State Circuits, vol. 25, Dec. 1990, pp. 1379-1384.
4. P. Kinget and M. Steyaert, "Impact of transistor mismatch on the speed-Accuracy-power trade-off of analog CMOS circuits", Proceedings CICC 1996, pp.333-336.
5. K. Uyttenhove and M. Steyaert, "Speed-Power-Accuracy trade-off in high-speed ADC's: what about nano-electronics?", Proceedings 2001 CICC, pp. 341-344.
6. M.J.M. Pelgrom, "A/D conversion and system considerations", in High Speed Data Converters, MEAD Microelectronics, Monterey, CA, Nov. 2000.
7. R.H. Walden, "Analog-to-Digital converter survey and analysis", IEEE Journal on Selected Areas in Communications, vol. 17, April 1999, pp. 539-550.