Measurement and spice prediction of sub-picosecond clock jitter in A/D converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Zanchi, A ^a   Papantonopoulos, I ^a   Tsay, F ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; JITTER; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

SPICE PREDICTION;

ANALOG TO DIGITAL CONVERSION;

EID: 0038757998     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. Moreland C., Murden F., Elliott M., Young J., Hensley M., and Stop R. "A 14b 100Msample/s subranging ADC", IEEE Journal of Solid-State Circuits, 35(12):1791-1798, 2001.
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9. TI Spice training manual, Texas Instruments Inc., 1999.