Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform

ACM SIGPLAN Notices

Volumn 39, Issue 11, 2004, Pages 144-155

  Wang, Perry H ^a   Collins, Jamison D ^a   Wang, Hong ^a   Kim, Dongkeun ^a,b   Greene, Bill ^a   Chan, Kai Ming ^a   Yunus, Aamir B ^a   Sych, Terry ^a   Moore, Stephen F ^a   Shen, John P ^a  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

Cache miss prefetching; DB2 database; Helper thread; Itanium processor; Multithreading; PAL; Switch on event

Indexed keywords

BENCHMARKING; BUFFER STORAGE; COMPUTER OPERATING SYSTEMS; DATABASE SYSTEMS; DECISION SUPPORT SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS; SWITCHING; VIRTUAL REALITY;

CACHE MISS PREFETCHING; DB2 DATABASE; HELPER THREADING; ITANIUM PROCESSOR; PROCESSOR ABSTRACTION LAYER (PAL); SWITCH ON-EVENT; VIRTUAL MULTITHREADING (VMT);

MICROPROCESSOR CHIPS;

EID: 19944428009     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/1037187.1024411     Document Type: Conference Paper

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