An advanced optimizer for the IA-64 architecture

IEEE Micro

Volumn 20, Issue 6, 2000, Pages 60-68

  Krishnaiyer, Rakesh ^a   Kulkarni, Dattatraya ^a   Lavery, Daniel ^a,b   Li, Wei ^a,b   Lim, Chu Cheow ^a   Ng, John ^a   Sehr, David ^a,b  

^a INTEL CORPORATION   (United States)

^b Intel ^*

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; HEURISTIC PROGRAMMING; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

DATA SPECULATION; INSTRUCTION LEVEL PARALLELISM; LOOP FUSION TECHNIQUE; PARTIAL DEAD STORE ELIMINATION; PARTIAL REDUNDANCY ELIMINATION;

PROGRAM COMPILERS;

EID: 0034318203     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.888704     Document Type: Article

References (7)

1. C. Dulong, "The IA-64 Architecture at Work," Computer, July 1998, pp. 24-32.
2. J. Huck et al., "Introducing the IA-64 Architecture," IEEE Micro, Sept.-Oct. 2000, pp. 12-23.
3. F. Chow et al., "A New Algorithm for Partial Redundancy Elimination Based on SSA Form," Proc. ACM SIGPLAN 97 Conf. Programming Language Design and Implementation, ACM, New York, 1997, pp. 273-286.
4. S. Muchnik, Advanced Compiler Design and Implementation, Morgan Kaufman, San Francisco, Calif., 1997.
5. D. Gallagher, Memory Disambiguation to Facilitate Instruction-Level Parallelism Compilation, PhD thesis, Dept. Electrical and Computer Eng., Univ. of Illinois at Urbana-Champaign, 1995.
6. R. Ju, J. Collard, and K. Oukbir, "Probabilistic Memory Disambiguation and Its Application to Data Speculation," Proc. Third Workshop Interaction Between Compilers and Computer Architectures, Univ. Minnesota, Minneapolis St. Paul, Oct. 1998.
7. B.R. Rau, "Data Flow and Dependence Analysis for Instruction-Level Parallelism," Proc. Fourth Int'l Workshop Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science 589, Springer-Verlag, Berlin, 1992, pp. 236-250.