Intel IA-64 compiler code generator

IEEE Micro

Volumn 20, Issue 5, 2000, Pages 44-53

  Bharadwaj, Jay ^a   Chen, William Y ^b   Chuang, Weihaw ^c   Hoflehner, Gerolf ^d   Menezes, Kishore ^e   Muthukumar, Kalyan ^f   Pierce, Jim ^g  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^e NORTH CAROLINA STATE UNIVERSITY   (United States)

^f UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^g UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED LOAD ADDRESS TABLE (ALAT); ELECTRON CODE GENERATORS (ECG); INSTRUCTION LEVEL PARALLELISM (ILP);

CODES (SYMBOLS); COMPUTER SYSTEMS PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; QUERY LANGUAGES; RESPONSE TIME (COMPUTER SYSTEMS); SOFTWARE ENGINEERING;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0034273823     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.877949     Document Type: Article

References (15)

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