Standard cell layout with regular contact placement

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 3, 2004, Pages 375-383

  Wang, Jun ^a   Wong, Alfred K ^b   Lam, Edmund Y ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b Fortis Systems Inc   (United States)

Author keywords

Double exposure; Fabrication friendly layout; Low k1 lithography; Regularly placed contact; RETs; Standard cells

Indexed keywords

FIR FILTERS; IMAGING TECHNIQUES; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LITHOGRAPHY; OPTIMAL SYSTEMS; PHASE SHIFT; STATIC RANDOM ACCESS STORAGE;

DOUBLE EXPOSURE; FABRICATION-FRIENDLY LAYOUT; LOW Κ1 LITHOGRAPHY; REGULARLY PLACED CONTACT; RESOLUTION ENHANCEMENT TECHNIQUES (RET); RET; STANDARD CELLS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 4344694445     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.831522     Document Type: Conference Paper

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