A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 4, 2005, Pages 813-819

  Nagata, Makoto ^a   Okumoto, Takeshi ^b   Taki, Kazuo ^a,c  

^a KOBE UNIVERSITY   (Japan)

^b PANASONIC CORPORATION   (Japan)

^c AIL Corporation   (Japan)

Author keywords

Embedded detector; Ground noise; Power supply noise; Signal integrity; Substrate noise

Indexed keywords

ENHANCED DETECTORS; GROUND NOISE; NOISE DISTRIBUTION; POWER SUPPLY; SIGNAL INTEGRITY; SUBSTRATE NOISE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DETECTORS; ELECTRIC POTENTIAL; LOGIC GATES; SPURIOUS SIGNAL NOISE; SUBSTRATES;

POWER SUPPLY CIRCUITS;

EID: 18744366707     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845559     Document Type: Conference Paper

References (12)

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