A built-in technique for probing power-supply noise distribution within large-scale digital integrated circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 98-101

  Okumoto, Takeshi ^a   Nagata, Makoto ^a   Taki, Kazuo ^a  

^a KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTOR CIRCUITS; DIGITAL INTEGRATED CIRCUITS; LSI CIRCUITS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; SUBSTRATES; WAVEFORM ANALYSIS;

DIGITAL CORES; DYNAMIC POWER SUPPLY; NOISE PROBING; POWER ANALYSIS TOOLS;

POWER SUPPLY CIRCUITS;

EID: 4544330484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R. Ho et al., "Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits," Symp. VLSI Circuits, June 1998, pp.138-139.
2. M. Takamiya et al., "An On-chip 100GHz-Sampling Rate 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator," ISSCC Dig. Tech. Papers, Feb. 2002, pp.182-183.
3. Y. Zheng and K. Shepard, "On-Chip Oscilloscopes for Non-invasive Time-Domain Measurement of Waveforms in Digital Integrated Circuits," IEEE Trans. VLSI Systems, June 2003, pp. 336-344.
4. M. Heijningen et al., "Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates," IEEE J. Solid-State Circ., July 2000, pp. 1002-1008.
5. M. Nagata et al., "Measurements and Analyses of Substrate Noise Waveform in Mixed-Signal IC Environment," IEEE Trans. CAD, June 2000, pp. 671-678.