Dynamic power-supply and well noise measurement and analysis for high frequency body-biased circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 94-97

  Shimazaki, Kenji ^a   Nagata, Makoto ^b   Okumoto, Takeshi ^b   Hirano, Shouzou ^a   Tsujikawa, Hiroyuki ^a  

^a PANASONIC CORPORATION   (Japan)

^b KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DETECTOR CIRCUITS; LSI CIRCUITS; ROBUSTNESS (CONTROL SYSTEMS); SPURIOUS SIGNAL NOISE; SUBSTRATES; WAVEFORM ANALYSIS;

DYNAMIC POWER SUPPLY; HIGH FREQUENCY BODY-BIASED CIRCUITS; PARASITIC EXTRACTORS; WELL NOISE;

POWER SUPPLY CIRCUITS;

EID: 4544377993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Tawfik Rahal-Arabi, et al, "Design & Validation of the Pentium III and Pentium 4 Processors Power Delivery", VLSI symposium C16P4
2. M. Nagata, et al., "Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment", IEEE Trans. CAD, Vol. 19, No. 6, pp. 671-678, June 2000
3. M. Takamiya, et al., "An On-chip 100GHz-Sampling Rate 8-channel Sampling Oscilloscope with Embedded Sampling Clock Generator", ISSCC Digest of Technical Papers, pp.182-183, Feb. 2002.
4. S. Narendra, et al., "1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS", ISSCC Digest of Technical Papers, pp.270-271, Feb. 2002
5. M. Nagata, et al., "Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits", Symp. VLSI Circuits, pp. 159-162, June 2001.