The leading edge of production wafer probe test technology

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1168-1195

  Mann, William R ^a   Taber, Frederick L ^b   Seitzer, Philip W ^c   Broz, Jerry J ^d  

^a Rockwell International   (United States)

^b IBM MICROELECTRONICS   (United States)

^c AGERE SYSTEMS   (United States)

^d International Test Solutions   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COBRA PROBE TECHNOLOGY; MICROELECTRONIC WAFERS; PARASITIC IMPEDANCE; THERMAL PACKAGE;

COSTS; DIES; ELECTRIC IMPEDANCE; FLIP CHIP DEVICES; METALLIZING; MICROELECTRONICS; MICROPROCESSOR CHIPS; PROBES; SEMICONDUCTOR MATERIALS; SOLDERING;

WSI CIRCUITS;

EID: 18144410978     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. U.S. Patent 4027935, June 1977
2. J.J. Broz J.C. Andersen, and R.M. Rincon, "Reducing device yield fallout at wafer level test with electro-hydrodynamic (EHD) cleaning", International Test Conference, September 2000.
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17. B. R. Benware, R. Madge, C. Lu, and C. Daasch, "Effective Comparison of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs," VLSI Test Symposium, April 2003, pp. 39-46.
18. C. Schuermyer, B. Benware, K. Cota, R. Madge, R. Daasch, and L. Ning, "Screening VDSM Outliers using Normal and Sub-threshold Supply Voltage IDDQ," International Test Conference, September 2003, pp. 556-573.
19. R.C. Aitken, "Test Generation and Fault Modeling for Stress Testing," International Symposium on Quality Electronic Designs, March 2002, pp. 95-99.
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