Burn-in failures and local region yield: An integrated yield-reliability model

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 326-332

  Barnett, T S ^a   Singh, A D ^a   Nelson, V P ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINS; COMPUTER SIMULATION; CRYSTAL DEFECTS; FAILURE ANALYSIS; MATHEMATICAL MODELS; MULTICHIP MODULES; POISSON DISTRIBUTION; RELIABILITY THEORY;

BURN-IN FAILURES; INTEGRATED YIELD RELIABILITY MODEL; LOCAL REGION YIELD; SEMICONDUCTOR WAFERS;

INTEGRATED CIRCUIT TESTING;

EID: 0035013704     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. On optimizing VLSI testing for product quality using die-yield prediction
2. Exploiting defect clustering to screen bare die for infant mortality failures: An experimental study
3. Binning for IC quality: Experimental studies on the SEMATECH data
4. Screening for known good die (KGD) based on defect clustering: An experimental study
5. Microprocessor reliability performance as a function of die location for a 0.25μ, five layer metal CMOS logic process
6. Reliability defect detection and screening during processing-theory and implementation
7. Relation between yield and reliability of integrated circuits: Experimental results and application to continuous early failure rate reduction programs
8. Impact of screening of latent defects at electrical test on the yield-reliability relation and application to burn-in elimination
9. Integrated circuit yield statistics
10. Correlation analysis of particle clusters on integrated circuit wafers
11. Yield models for defect tolerant VLSI circuits: A review