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0034459843
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Intrinsic Leakage in Deep Submicron CMOS IC Measurement Based Test Solutions
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December
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A, Keshavarzi, K. Roy, C.F. Hawkins, "Intrinsic Leakage in Deep Submicron CMOS IC Measurement Based Test Solutions," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 717-723, December 2000
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Keshavarzi, A.1
Roy, K.2
Hawkins, C.F.3
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2
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0033307906
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A Histogram Based Procedure for Current Testing of Active Defects
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October
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C. Thibeault, "A Histogram Based Procedure for Current Testing of Active Defects," International Test Conference, pp. 719-723, October, 1999
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International Test Conference
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Thibeault, C.1
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3
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0034483640
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Variance Reduction Using Wafer Patterns in IDDQ Data
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October
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W.R. Daasch, J. McNames, D. Bockelman, K. Cota, R. Madge, "Variance Reduction Using Wafer Patterns in IDDQ Data," International Test Conference, pp. 189-198, October 2000
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Daasch, W.R.1
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Cota, K.4
Madge, R.5
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4
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0033326421
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Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
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October
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P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, D. Wiseman, "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing," International Test Conference, pp. 738-746, October 1999
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International Test Conference
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Maxwell, P.1
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Jaarsma, N.5
Quach, M.6
Wiseman, D.7
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5
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51449088512
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Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies
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April
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R. Madge, M. Rehani, K. Cota, R. Daasch, "Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies," VLSI Test Symposium, pp. 69-74, April 2002
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Madge, R.1
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Daasch, R.4
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6
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0036444846
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Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data
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Oct.
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W.R. Daasch, K. Cota, J. McNames, R. Madge, "Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data," International. Test Conference, pp. 1240-1248, Oct. 2002
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International. Test Conference
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Daasch, W.R.1
Cota, K.2
McNames, J.3
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7
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67249089270
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Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction
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April
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S. Sabade, H. Walker, "Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction," VLSI Test Symposium, pp. 81-86, April 2002
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VLSI Test Symposium
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Sabade, S.1
Walker, H.2
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8
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0032319930
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Experimental Results for IDDQ and VLV Testing
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April
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J.T.-Y. Chang, C-W Tseng; Y-C Chu; S. Wattal, M. Partell, E.J. McCluskey, Experimental Results for IDDQ and VLV Testing," VLSI Test Symposium, pp. 118-123, April 1998
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Chang, J.T.-Y.1
Tseng, C.-W.2
Chu, Y.-C.3
Wattal, S.4
Partell, M.5
McCluskey, E.J.6
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9
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84948420320
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Performance Comparison of VLV, ULV, and ECR Tests
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April
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J. Wanli, E. Peterson, "Performance Comparison of VLV, ULV, and ECR Tests", VLSI Test Symposium, pp. 31-36, April 2002
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VLSI Test Symposium
, pp. 31-36
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Wanli, J.1
Peterson, E.2
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10
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0031382110
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Intrinsic Leakage in Low Power Deep Submicron CMOS ICs
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Nov.
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A. Keshavarzi, K. Roy, C.F. Hawkins, "Intrinsic Leakage in Low Power Deep Submicron CMOS ICs", International Test Conference, pp. 146-155, Nov. 1997
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Keshavarzi, A.1
Roy, K.2
Hawkins, C.F.3
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