Yield-reliability modeling: Experimental verification and application to burn-in reduction

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 75-80

  Barnett, T S ^a   Singh, A D ^a   Grady, M ^b   Purdy, K ^b  

^a AUBURN UNIVERSITY   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Microelectronics; Microprocessors; Predictive models; Probes; Semiconductor device manufacture; Semiconductor device modeling; Sorting; Stress; Testing; Virtual manufacturing

Indexed keywords

AGILE MANUFACTURING SYSTEMS; BINS; DIES; MANUFACTURE; MICROELECTRONICS; MICROPROCESSOR CHIPS; PROBES; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SILICON WAFERS; SORTING; STRESSES; TESTING;

EXPERIMENTAL VERIFICATION; IBM MICROELECTRONICS; INFANT MORTALITY FAILURES; MICROPROCESSOR UNITS; PREDICTIVE MODELS; RANDOMLY DISTRIBUTED; SEMI-CONDUCTOR WAFER; VIRTUAL MANUFACTURING;

SEMICONDUCTOR DEVICE MODELS;

EID: 0010401965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011114     Document Type: Conference Paper

References (8)

1. Hance H. Huston and C. Patrick Clarke, "Reliability Defect Detection and Screening During Processing-Theory and Implementation," Proceedings International Reliability Physics Symposium, 1992, pp. 268-275.
2. A.D. Singh and C.M. Krishna, "On Optimizing VLSI Testing for Product Quality Using Die-Yield Prediction", IEEE Transactions on CAD, Vol. 12, No. 5, May 1993, pp. 695-709.
3. T.S. Barnett, A.D. Singh and V.P. Nelson, "Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model", Proceedings 2001 VLSI Test Symposium, May 2001, pp. 326-332.
4. W. Riordan, R. Miller, J. Sherman, J. Hicks, "Microprocessor Reliability Performance as a Function of Die Location for a 0.25μ, Five Layer Metal CMOS Logic Process", Proceedings International Reliability Physics Symposium, 1999, pp. 1-11.
5. C.H.Stapper, F.M. Armstrong, and K. Saji, "Integrated Circuit Yield Statistics", Proceedings of IEEE, April 1983, pp. 453-470.
6. I. Koren and Z. Koren, "Defect Tolerant VLSI Circuits: Techniques and Yield Analysis," Proceedings of the IEEE, Vol. 86, Sept. 1998, pp. 1817-1836.
7. I. Koren and C.H. Stapper, "Yield Models for Defect Tolerant VLSI Circuits: A Review," Defect and Fault Tolerance in VLSI Systems, Vol. 1, I. Koren (ed.), Plenum, 1989, pp. 1-21.
8. T.S. Barnett, A.D. Singh and V.P. Nelson, "Estimating Burn-In Fall-Out for Redundant Memory", Proceedings 2001 International Test Conference, to appear, November 2001.