MRAM defect analysis and fault modeling

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 124-133

  Su, Chin Lung ^a   Huang, Rei Fu ^a   Wu, Cheng Wen ^a   Hung, Chien Chung ^b   Kao, Ming Jer ^b   Chang, Yeong Jar ^b   Wu, Wen Ching ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CORRELATION METHODS; ELECTRIC FAULT CURRENTS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

KINK FAULTS; MAGNETIC TUNNEL JUNCTION (MTJ); NON-VOLATILE MEMORIES; SYSTEM ON CHIP (SOC);

INTEGRATED CIRCUIT TESTING;

EID: 18144400442     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

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