메뉴 건너뛰기




Volumn , Issue , 2003, Pages 29-38

Fault Pattern Oriented Defect Diagnosis for Memories

Author keywords

Bitmap; Failure analysis (FA); Fault pattern; Memory diagnostics; Memory testing; Semiconductor memory

Indexed keywords

COMPUTER SIMULATION; COMPUTER TESTING; MICROPROCESSOR CHIPS;

EID: 0142153748     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (23)

References (19)
  • 1
    • 0036044639 scopus 로고    scopus 로고
    • Embedded infrastructure IP for SOC yield improvement
    • New Orleans, June
    • Y. Zorian, "Embedded infrastructure IP for SOC yield improvement", in Proc. IEEE/ACM Design Automation Conf. (DAC), New Orleans, June 2002, pp. 709-712.
    • (2002) Proc. IEEE/ACM Design Automation Conf. (DAC) , pp. 709-712
    • Zorian, Y.1
  • 3
    • 0035337753 scopus 로고    scopus 로고
    • Using electrical bitmap results from embedded memory to enhance yield
    • May
    • J. Segal, A. Jee, D. Lepejian, and B. Chu, "Using electrical bitmap results from embedded memory to enhance yield", IEEE Design & Test of Computers, vol. 15, no. 3, pp. 28-39, May 2001.
    • (2001) IEEE Design & Test of Computers , vol.15 , Issue.3 , pp. 28-39
    • Segal, J.1    Jee, A.2    Lepejian, D.3    Chu, B.4
  • 4
    • 0142237097 scopus 로고    scopus 로고
    • An overview of advanced failure analysis techniques for Pentium and Pentium Pro microprocessors
    • Y. E. Hong, L. S. Leong, W. Y. Choong, L. C. Hou, and M. Adnan, "An overview of advanced failure analysis techniques for Pentium and Pentium Pro microprocessors", Intel Technology Journal, , no. 2, 1998.
    • (1998) Intel Technology Journal , Issue.2
    • Hong, Y.E.1    Leong, L.S.2    Choong, W.Y.3    Hou, L.C.4    Adnan, M.5
  • 5
    • 0035017465 scopus 로고    scopus 로고
    • Enabling embedded memory diagnosis via test response compression
    • Marina Del Rey, California, Apr.
    • J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, "Enabling embedded memory diagnosis via test response compression", in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 292-298.
    • (2001) Proc. IEEE VLSI Test Symp. (VTS) , pp. 292-298
    • Chen, J.T.1    Rajski, J.2    Khare, J.3    Kebichi, O.4    Maly, W.5
  • 6
    • 0032317506 scopus 로고    scopus 로고
    • Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
    • Washington, DC, Oct.
    • I. Schanstra, D. Lukita, A. J. van de Goor, K. Veelenturf, and P. J. van Wijnen, "Semiconductor manufacturing process monitoring using built-in self-test for embedded memories", in Proc. Int. Test Conf. (ITC), Washington, DC, Oct. 1998, pp. 872-881.
    • (1998) Proc. Int. Test Conf. (ITC) , pp. 872-881
    • Schanstra, I.1    Lukita, D.2    Van de Goor, A.J.3    Veelenturf, K.4    Van Wijnen, P.J.5
  • 8
    • 0024124138 scopus 로고
    • Fault modeling and test algorithm development for static random access memories
    • R. Dekker, F. Beenker, and L. Thijssen, "Fault modeling and test algorithm development for static random access memories", in Proc. Int. Test Conf. (ITC), 1988, pp. 343-352.
    • (1988) Proc. Int. Test Conf. (ITC) , pp. 343-352
    • Dekker, R.1    Beenker, F.2    Thijssen, L.3
  • 10
    • 0033749132 scopus 로고    scopus 로고
    • Simulation-based test algorithm generation for random access memories
    • Montreal, Apr.
    • C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, "Simulation-based test algorithm generation for random access memories", in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291-296.
    • (2000) Proc. IEEE VLSI Test Symp. (VTS) , pp. 291-296
    • Wu, C.-F.1    Huang, C.-T.2    Cheng, K.-L.3    Wu, C.-W.4
  • 13
    • 0035015860 scopus 로고    scopus 로고
    • Automatic generation of diagnostic March tests
    • Marina Del Rey, California, Apr.
    • D. Niggemeyer and E. Rudnick, "Automatic generation of diagnostic March tests", in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 299-304.
    • (2001) Proc. IEEE VLSI Test Symp. (VTS) , pp. 299-304
    • Niggemeyer, D.1    Rudnick, E.2
  • 16
    • 0034505514 scopus 로고    scopus 로고
    • An experimental analysis of spot defects in SRAMs: Realistic fault models and tests
    • Taipei, Dec.
    • S. Hamdioui and A. J. van de Goor, "An experimental analysis of spot defects in SRAMs: realistic fault models and tests", in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 131-138.
    • (2000) Proc. Ninth IEEE Asian Test Symp. (ATS) , pp. 131-138
    • Hamdioui, S.1    Van de Goor, A.J.2
  • 18
    • 0036732498 scopus 로고    scopus 로고
    • Resistance characterization for weak open defects
    • Sept.-Oct.
    • R. R. Montanes, J. P. de Gyvez, and P. Volf, "Resistance characterization for weak open defects", IEEE Design & Test of Computers, vol. 19, no. 5, pp. 18-26, Sept.-Oct. 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.5 , pp. 18-26
    • Montanes, R.R.1    De Gyvez, J.P.2    Volf, P.3
  • 19
    • 0033357317 scopus 로고    scopus 로고
    • Defining SRAM resistive defects and their simulation stimuli
    • Shanghai, Nov.
    • A. J. van de Goor and J. E. Simonse, "Defining SRAM resistive defects and their simulation stimuli", in Proc. Eighth IEEE Asian Test Symp. (ATS), Shanghai, Nov. 1999, pp. 33-40.
    • (1999) Proc. Eighth IEEE Asian Test Symp. (ATS) , pp. 33-40
    • Van de Goor, A.J.1    Simonse, J.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.