MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 156-157

  Honda, Takeshi ^a   Sakimura, Noboru ^a   Sugibayashi, Tadahiko ^a   Miura, Sadahiko ^a   Numata, Hideaki ^a   Hada, Hiromitsu ^a   Tahara, Shu Ichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; MAGNETIZATION; NORMAL DISTRIBUTION; SEMICONDUCTOR DIODES; STATISTICAL METHODS; THERMAL EFFECTS;

MAGNETIZATION REVERSAL CURRENT; MAGNETORESISTIVE RANDOM ACCESS STORAGE; MULTIPLE WRITE FAILURE; SOFTWARE PACKAGE SPICE; THERMAL VARIATION;

RANDOM ACCESS STORAGE;

EID: 0142169295     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R. Scheuerlein et al., "A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell", ISSCC Dig. Tech. Papers, pp. 128-129, Feb. 2000.
2. P.K. Naji et al., "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM", ISSCC Digest of Technical Papers, pp. 122-123, Feb. 2001.
3. M. Bhattacharyya et al., "Thermal Variation in Switching Fields for Sub-Micron MRAM Cells", IEEE Trans. Mag. 37 1970 (2001).