On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 737-744

  Tekumalla, Ramesh C ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; LOGIC DESIGN; SHIFT REGISTERS;

MULTIPLE INPUT SHIFT REGISTERS (MISR);

BUILT-IN SELF TEST;

EID: 0142215970     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. R.C. Aitken and V.K. Agarwal, "A diagnosis method using pseudo-random vectors without intermediate signatures", Proc. Intl. Conf. Computer Aided Design, pp. 574-577, 1989.
2. S. Kundu, "On diagnosis of faults on a scan-chain", Proc. VLSI Test Symposium, pp. 303-308, 1993.
3. T.R. Damarla, C.E. Stroud and A. Sathaye, "Multiple error detection and identification via signature analysis", Journal of Electronic Testing: Theory and Applications, vol. 7, no. 3, pp. 193-207, 1995.
4. Y. Wu and S. Adham, "BIST fault diagnosis in scan-based VLSI environment", Proc. Intl. Test Conf., pp. 48-57, 1996.
5. S.-Y. Huang et. al., "Error Tracer: A fault simulation based approach to design error diagnosis", Proc. Intl. Test Conf., pp. 974-981, 1997.
6. J. Rajski and J. Tyszer, "Fault diagnosis in scan based BIST", Proc. Intl. Test Conf., pp. 894-902, 1997.
7. A. Veneris and I.N. Hajj, "Design error diagnosis and correction via test vector simulation", IEEE Trans. CAD, 18(12):1803-1816, Dec. 1999.
8. J. Rajski and J. Tyszer, "Diagnosis of scan cells in BIST environment", IEEE Trans. Computers, vol. 48, Issue: 7, pp. 724-731, 1999.
9. S. Venkataraman and S.B. Drummonds, "A technique for logic fault diagnosis of interconnect open defects", Proc. VLSI Test Symposium, pp. 313-318, 2000.
10. S.-Y. Huang, "On improving the accuracy of multiple defect diagnosis", Proc. VLSI Test Symposium, pp. 34-39, 2001.
11. I. Bayraktaroglu and A. Orailoglu, "Diagnosis of scan based BIST: Reaching deep into signatures", Proc. Design Automation and Test in Europe, pp. 102-109, 2001.
12. R. Guo et. al., "A technique for fault diagnosis of defects in scan chains", Proc. Intl. Test Conf., pp. 268-277, 2001.
13. N. Sridhar and M.S. Hsiao, "On efficient error diagnosis of digital circuits", Proc. Intl. Test Conf., pp. 678-687, 2001.