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Volumn 2003-January, Issue , 2003, Pages 345-350

Improving diagnostic resolution of delay faults using path delay fault model

Author keywords

Automatic test pattern generation; Circuit faults; Delay; Failure analysis; Fault diagnosis; Fault location; Laboratories; Performance evaluation; Prototypes; Testing

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; FAILURE ANALYSIS; LABORATORIES; TESTING;

EID: 10444245390     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197673     Document Type: Conference Paper
Times cited : (9)

References (14)
  • 1
    • 0036444572 scopus 로고    scopus 로고
    • Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges
    • J. Saxena, et.al., "Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges", in Proc. Int. Test Conf., Oct. 2002, pp. 1120-1129.
    • Proc. Int. Test Conf., Oct. 2002 , pp. 1120-1129
    • Saxena, J.1
  • 4
    • 0035273034 scopus 로고    scopus 로고
    • Path Delay Fault Diagnosis and Coverage - A Metric and an Estimation Technique
    • March
    • M. Sivaraman and A. J. Strojwas, "Path Delay Fault Diagnosis and Coverage - A Metric and an Estimation Technique", IEEE Trans. Computer-Aided Design, vol. 20, no. 3, pp. 440-457, March 2001.
    • (2001) IEEE Trans. Computer-Aided Design , vol.20 , Issue.3 , pp. 440-457
    • Sivaraman, M.1    Strojwas, A.J.2
  • 6
    • 0035472653 scopus 로고    scopus 로고
    • Path Delay Fault Diagnosis in Combinational Circuits With Implicit Fault Enumeration
    • October
    • P. Pant, Y-C. Hsu, S. K. Gupta and A. Chatterjee," Path Delay Fault Diagnosis in Combinational Circuits With Implicit Fault Enumeration", IEEE Trans Computer-Aided Design, vol. 20, no. 10, pp. 1226-1235, October 2001.
    • (2001) IEEE Trans Computer-Aided Design , vol.20 , Issue.10 , pp. 1226-1235
    • Pant, P.1    Hsu, Y.-C.2    Gupta, S.K.3    Chatterjee, A.4
  • 9
    • 0024053829 scopus 로고
    • A Method of Fault Analysis for Test Generation and Fault Diagnosis
    • July
    • H. Cox and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis", IEEE Trans. Computer-Aided Design, vol. 7, no. 7, July 1988, pp. 813-833.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , Issue.7 , pp. 813-833
    • Cox, H.1    Rajski, J.2
  • 12
    • 0036443068 scopus 로고    scopus 로고
    • Finding a Small Set of Longest Testable Paths That Cover Every Gate
    • M. Sharma and J. H. Patel, "Finding a Small Set of Longest Testable Paths That Cover Every Gate", in Proc. Int. Test Conf., October 2002, pp. 974-982.
    • Proc. Int. Test Conf., October 2002 , pp. 974-982
    • Sharma, M.1    Patel, J.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.