Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 105-111

  Yan, Haihua ^a   Singh, Adit D ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC FAULT LOCATION; PARAMETER ESTIMATION; SIGNAL PROCESSING; SWITCHING;

DELAY FAULTS;

ELECTRIC FAULT CURRENTS;

EID: 0142153750     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. Singh, A.D., Yan, H., "Detecting Delay Defects in Slack Intervals using Multiple Higher Clock Frequencies and Results from Neighboring Die", Digest of Papers, European Test Workshop, 2003.
2. A.Pierzynska, and S.Pilarsky, "Non-Robust versus Robust", ITC, 1995.
3. J.L. Avra and E.J. McCluskey, "Synthesizing for Scan Dependence in Built-In Self-Testable Design", Proceedings ITC, 1993.
4. K.-T. Cheng, and C.-Lin, "Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST", Proceedings ITC, 1995, pp. 506-514.
5. Butler, K., "Deep Submicron: Is Test Up To The Challenge?" Proceedings ITC, 1995, pp.923.
6. Oakland, S., "Why Would an ASIC Foundry Accept Anything Less than Full Scan?", Proceedings ITC, 1997.
7. B.Koenemann et al. "Delay Test: The Next Frontier for LSSD Test Systems", ITC, 1992, pp. 578-587.
8. Dervisoglu, B. and Strong, G., "Design For Testability : Using Scanpath Techniques for Path Delay Test and Measurement", IEEE ITC, 1991, pp. 365-374.
9. Varma, P., "On Path-Delay Testing in a Standard Scan Environment", International Test. Conference, 1994, pp. 164.
10. Savir, J., "Scan Latch Design for Delay Test", Proceedings International Test Conference, 1997.
11. Tekumalla, R., Menon, P., "Delay Testing with Clock Control: An Alternative to Enhanced Scan", Proceedings International Test Conference, 1997.
12. Smith, G.I., "Model for Delay Faults Based Upon Paths", Proceedings International Test Conference, pp.342-349, November 1985.
13. Lin, C.J. and Reddy, S.M., "On Delay Fault Testing in Logic Circuit", IEEE Transactions on CAD, pp. 694-703, Sept. 1987.
14. Savir, J. and Patil, S., "Broad-side Delay Test", IEEE Transactions on Computer-Aided Design, 13(8):1057-1064, August 1994.
15. McCluskey, E.J.,"Can DFT Totally Delete Traditional Functional Testing?" Proceedings International Test Conference, 2000.
16. Daasch, W., Cota, K., McNames, J., and Madge, R., "Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data", Proceedings International Test Conference, 2001, pp 92-100.