Routability-driven floorplanner with buffer block planning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 470-480

  Sham, Chiu Wing ^a   Young, Evangeline F Y ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Buffer planning; Computer aided design; Floor planning; Interconnect driven; Physical design; Very large scale integration (VLSI)

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; PROBABILITY; RECURSIVE FUNCTIONS; SIMULATED ANNEALING; VLSI CIRCUITS;

BUFFER BLOCK PLANNING; INTERCONNECT-DRIVEN; PHYSICAL DESIGN; ROUTABILITY-DRIVEN FLOORPLANNER;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037389454     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809649     Document Type: Article

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