Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 580-587

  Albrecht, C ^b   Kahng, A B ^a   Mandoiu I ^a   Zelikovsky, A ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF BONN   (Germany)

^c GEORGIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN; ECONOMIC AND SOCIAL EFFECTS; ELECTRONIC TRADING;

CAPACITY CONSTRAINTS; DELAY CONSTRAINTS; GLOBAL ROUTING; LAYER ASSIGNMENT; MULTI-COMMODITY FLOW; PIN ASSIGNMENT; TIMING-DRIVEN; TRADE-OFF CURVES;

EMBEDDED SYSTEMS;

EID: 0037999032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994986     Document Type: Conference Paper

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