Optimal spacing and capacitance padding for general clock structures

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 115-119

  Lee, Yu Min ^a   Lai, Hing Yin ^a   Chen, C C P ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Capacitance; Clocks; Delay effects; Laplace equations; Linear programming; Mathematical programming; Minimization; Power dissipation; Runtime; Topology

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; ENERGY DISSIPATION; LAPLACE EQUATION; LINEAR PROGRAMMING; MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; OPTIMIZATION; TOPOLOGY; WIRE;

DELAY EFFECTS; ELMORE DELAY MODEL; GLOBAL OPTIMAL SOLUTIONS; INDUSTRY EXAMPLES; LINEAR PROGRAMMING PROBLEM; PENTIUM III PROCESSOR; RUNTIMES; TUNING ALGORITHM;

CLOCKS;

EID: 0038674534     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913290     Document Type: Conference Paper

References (16)

1. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Pub. Company Inc., 1990.
2. C.P. Chen, Y.W Chang, and D. F. Wong, "Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation" DAC, 1996.
3. J. Chung and C.-K. Cheng, "Skew sensitivity minimization of buffered clock tree," Proc. ICCAD, pp. 280-283, 1994.
4. J. Cong and K.-S. Leung, "Optimal wiresizing under elmore delay model," IEEE TCAD 14(3), pp. 321-336, 1995.
5. D. Dobberpuhl and R. Witek, "A 200MHz 64B dual-issue CMOS microprocessor," Proc. IEEE ISSCC, pp. 106-107, 1992.
6. W. C. Elmore, "The transient response of damped linear networks with particular regard to wide band amplifiers," J. Applied Physics, 19(1), 1948.
7. M. A. B. Jackson, et al., "Clock routing for high performance ICs," Proc. DAC, pp. 573-579, June 1990.
8. D. G. Luenberger, Linear and Nonlinear Programming, Addison-Wesley Pub. Company Inc., 1984.
9. N. Menezes, R. Baldick, and L. T. Pillage, "A sequential quadratic programming approach to concurrent gate and wire-sizing," Proc. ICCAD, 1995.
10. N. Menezes, S. Pullela, F. Dartu, and L. T. Pillage, "RC interconnect syntheses - a moment fitting approach," Proc. ICCAD, Nov. 1994.
11. S. Pullela, N. Menezes, and L. T. Pillage, "Reliable non-zero skew clock trees using wire width optimization," Proc. 30th ACM/IEEE Design Automation Conference, pp. 165-170, June 1993.
12. S. S. Sapatnekar, "RC interconnect optimization under the Elmore delay model," Proc. ICCAD, pp. 387-391, 1994.
13. R.-S. Tasy, "Exact zero skew," IEEE TCAD, 1993.
14. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI design - A Systems Perspective, Addison-Wesley Pub. Company Inc., 1993.
15. Q. Zhu, W. W.-M. Dai, and J. G. Xi, "Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models," Proc. ICCAD, pp. 628-633, 1993.
16. L. T. Pillege, and R. A. Rohrer "Asymptotic waveform evaluation for timing analysis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April, 1990.