A path-based methodology for post-silicon timing validation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 713-720

  Lee, Leonard ^a   Wang, Li C ^a   Mak, T M ^b   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PATH RANKING; PATTERN DELAYS; SUBSETS; TIMING MODELS;

BENCHMARKING; COMPUTER SIMULATION; FREQUENCIES; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING; SILICON; STATISTICAL METHODS;

INTEGRATED CIRCUIT LAYOUT;

EID: 16244395473     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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