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Volumn , Issue , 2000, Pages 393-399
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On invalidation mechanisms for non-robust delay tests
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SIMULATION;
GATES (TRANSISTOR);
LOGIC CIRCUITS;
MOS DEVICES;
NAND CIRCUITS;
PROBABILITY;
INVALIDATION;
NONROBUST DELAY TESTS;
PATH DELAY FAULT;
INTEGRATED CIRCUIT TESTING;
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EID: 0034482994
PISSN: 10893539
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (20)
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References (17)
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