A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 3, 2005, Pages 736-743

  Kreienkamp, Rainer ^a   Langmann, Ulrich ^a   Zimmermann, Christoph ^a   Aoyama, Takuma ^a   Siedhoff, Hubert ^a  

^a RUHR UNIVERSITY BOCHUM   (Germany)

Author keywords

Analog quadrature phase interpolator; Chip to chip interconnects; CMOS; Half rate clock and data recovery

Indexed keywords

BIT ERROR RATE; DEMULTIPLEXING; ELECTRIC POTENTIAL; INTERPOLATION; JITTER; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

ANALOG QUADRATURE PHASE INTERPOLATORS; CHIP-TO-CHIP INTERCONNECTS; DATA RECOVERY; HALF-RATE CLOCK;

CMOS INTEGRATED CIRCUITS;

EID: 16244388280     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.843624     Document Type: Article

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