-
1
-
-
0027590694
-
Delta-Sigma modulation in fractional-N frequency synthesis
-
May
-
T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-Sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 553-559
-
-
Riley, T.A.D.1
Copeland, M.A.2
Kwasniewski, T.A.3
-
2
-
-
0032122640
-
An agile ISM band frequency synthesizer with built-in GMSK data modulation
-
July
-
N. Filiol, T. A. D. Riley, C. Plett, and M. A. Copeland, "An agile ISM band frequency synthesizer with built-in GMSK data modulation," IEEE J. Solid-State Circuits, vol. 33, pp. 998-1008, July 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 998-1008
-
-
Filiol, N.1
Riley, T.A.D.2
Plett, C.3
Copeland, M.A.4
-
3
-
-
0034430926
-
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b 3rd-order ΔΣ modulator
-
Oct.
-
W. Rhee, B. Song, and A. Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b 3rd-order ΔΣ modulator," IEEE J. Solid-State Circuits, vol. 35, pp. 271-350, Oct. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 271-350
-
-
Rhee, W.1
Song, B.2
Ali, A.3
-
4
-
-
0036539971
-
An 18-mW2.5-GHz/900-MHz BiCMOS dual frequency Synthesizer with <10-Hz RF carrier resolution
-
Apr.
-
W. Rhee et al., "An 18-mW2.5-GHz/900-MHz BiCMOS dual frequency Synthesizer with <10-Hz RF carrier resolution," IEEE J. Solid-State Circuits, vol. 37, pp. 515-520, Apr. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.37
, pp. 515-520
-
-
Rhee, W.1
-
5
-
-
0034428331
-
An integrated 2.5 GHz ΣΔ frequency synthesizer with 5-ms settling and 2-Mb/s closed loop modulation
-
Feb.
-
S. Willingham et al., "An integrated 2.5 GHz ΣΔ frequency synthesizer with 5-ms settling and 2-Mb/s closed loop modulation," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 200-201.
-
(2000)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 200-201
-
-
Willingham, S.1
-
6
-
-
0031332530
-
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
-
Dec.
-
M. Perrott, T. Tewksbury, and C. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 2048-2060
-
-
Perrott, M.1
Tewksbury, T.2
Sodini, C.3
-
7
-
-
0035335391
-
A 1.8 GHz self-calibrated phase-locked loop with precise I/Q matching
-
May
-
C. Park, O. Kim, and B. Kim, "A 1.8 GHz self-calibrated phase-locked loop with precise I/Q matching," IEEE J. Solid-State Circuits, vol. 36, pp. 777-783, May 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 777-783
-
-
Park, C.1
Kim, O.2
Kim, B.3
-
8
-
-
0035334850
-
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique
-
May
-
K. Lee et al., "A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique," IEEE J. Solid-State Circuits, vol. 36, pp. 800-809, May 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 800-809
-
-
Lee, K.1
-
9
-
-
0035368885
-
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
-
June
-
L. Sun and T. A. Kwasniewski, "A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator," IEEE J. Solid-State Circuits, vol. 36, pp. 910-916, June 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 910-916
-
-
Sun, L.1
Kwasniewski, T.A.2
-
10
-
-
0031075618
-
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme
-
Feb.
-
S. J. Lee, B. Kim, and K. Lee, "A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme," IEEE J. Solid-State Circuits, vol. 32, pp. 289-291, Feb. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 289-291
-
-
Lee, S.J.1
Kim, B.2
Lee, K.3
-
12
-
-
0003573558
-
-
Piscataway, NJ: IEEE Press
-
S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta - Sigma Data Converters Theory, Design and Simulation. Piscataway, NJ: IEEE Press, 1997.
-
(1997)
Delta - Sigma Data Converters Theory, Design and Simulation
-
-
Norsworthy, S.R.1
Schreier, R.2
Temes, G.C.3
-
13
-
-
0030145220
-
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
-
May
-
P. Larsson, "High-speed architecture for a programmable frequency divider and a dual-modulus prescaler," IEEE J. Solid-State Circuits, vol. 31, pp. 744-748, May 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 744-748
-
-
Larsson, P.1
-
14
-
-
0036640950
-
A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800
-
July
-
B. D. Muer and M. Steyaert, "A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuits, vol. 37, pp. 835-844, July 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 835-844
-
-
Muer, B.D.1
Steyaert, M.2
|