Low-Power Fully Integrated 10-Gb/s SONET/SDH Transceiver in 0.13-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 10, 2003, Pages 1595-1601

  Henrickson, Lindor ^a   Shen, David ^b   Nellore, Uno ^a   Ellis, Alan ^a   Oh, Joong ^a   Wang, Hui ^c   Capriglione, Giovanni ^a   Atesoglu, Ali ^a   Yang, Alice ^a   Wu, Peter ^a   Quadri, Syed ^a   Crosbie, David ^a  

^a Agere Systems   (United States)

^b IRF Semiconductor USA   (United States)

^c MARVELL SEMICONDUCTOR INC   (United States)

Author keywords

Broad band communication; CMOS integrated circuits; Optical communication; Phase locked loops; SONET

Indexed keywords

DEMULTIPLEXING; JITTER; MULTIPLEXING; OPTICAL COMMUNICATION; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK DRIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 0141920421     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.817586     Document Type: Article

References (16)

1. Teleordia Technologies, GR-253-CORE Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, 2000.
2. W. J. Goralski, SONET, 2nd ed. New York: McGraw-Hill, 2000.
3. H. Cong, S. M. Logan, M. J. Loinaz, K. O'Brien, E. E. Perry, G. D. Pol-hemus, J. E. Scoggins, K. P. Snowdon, and M. G. Ward, "A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25 μm SiGe BiCMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1946-1953, Dec. 2001.
4. L. I. Andersson, B. Rudberg, P. Lewin, M. Reed, S. Planer, and S. Sundaram, "Silicon bipolar chipset for SONET/SDH 10-Gb/s fiber-optic communication links," IEEE J. Solid-State Circuits, vol. 30, pp. 210-218, Mar. 1995.
5. A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, and F. Masuoka, "0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation," IEEE J. Solid-State Circuits, vol. 36, pp. 988-996, June 2001.
6. A. Momtaz, J. Cao, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, W. Tan, I. Fujimori, and Y. Cai, "A fully integrated SONET OC-48 transceiver in standard CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1964-1973, Dec. 2001.
7. M. Green, A. Momtaz, K. Vakilian, X. Wang, K. C. Jen, D. Chung, J. Cao, M. Caresosa, A. Hairepetian, I. Fujimori, and Y. Cai, "OC-192 transmitter in standard 0.18-μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, p. 248.
8. J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design. Boston, MA: Kluwer, 1998.
9. A. Hajimiri and T. H. Lee, Low Noise Oscillators. Boston, MA: Kluwer, 1999.
10. D. H. Wolaver, Phase-Locked Loop Circuit Design. Englewood Cliffs, NJ: Prentice-Hall, 1991.
11. E. Sackinger and W. C. Fischer, "A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers," IEEE J. Solid-State Circuits, vol. 35, pp. 1884-1888, Dec. 2000.
12. J. D. H. Alexander, "Clock recovery from random binary signals," Electron. Lett., vol. 11, p. 541, 1975.
13. R. C. Walker, C. Stout, J. Wu, B. Lai, C. Yen, T. Hornak, and P. Petruno, "A two-chip 1.5-GBd serial link interface," IEEE J. Solid-State Circuits, vol. 27, pp. 1805-1811, Dec. 1992.
14. Y. M. Greshishchev, P. Schvan, J. L. Showell, M. L. Xu, J. J Ojha, and J. E. Rogers, "A fully integrated SiGe receiver IC for 10-Gb/s data rate," IEEE J. Solid-State Circuits, vol. 35, pp. 1949-1957, Dec. 2000.
15. J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector," IEEE J. Solid-State Circuits, vol. 38, pp. 13-21, Jan. 2003.
16. J. Cao, A. Momtaz, K. Vakilian, M. Green, D. Chung, K. C. Jen, M. Caresosa, B. Tan, I. Fujimori, and A. Hairapetian, "OC-192 receiver in standard 0.18-μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, p. 250.