A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1666-1672

  Yamaguchi, Kouichi ^b   Fukaishi, Muneo ^a,b   Sakamoto, Takehiko ^b   Akiyama, Naoto ^b   Nakamura, Kazuyuki ^a,b  

^a IEEE

^b NEC CORPORATION   (Japan)

Author keywords

Clock and data recovery; DLL; Multichannel; Multiphase clock; Nonfeedback; Phase interpolator; Quadrature clock

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION; MATHEMATICAL MODELS; PHASE LOCKED LOOPS; SIGNAL RECEIVERS;

CHANNEL RECEIVER; FOUR PHASE CLOCK DISTRIBUTION; MULTIPHASE CLOCK GENERATOR; PHASE CLOCK GENERATOR; SINGLE-PHASE CLOCK DISTRIBUTION;

TIMING CIRCUITS;

EID: 0035505388     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962286     Document Type: Article

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