20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1611-1618

  Fukaishi, Muneo ^a,b   Nakamura, Kazuyuki ^a   Heiuchi, Hideki ^a   Hirota, Yoshinori ^a   Nakazawa, Yoetsu ^a   Ikeno, Hidenori ^a   Hayama, Hiroshi ^a   Yotsuyanagi, Michio ^a  

^a NEC CORPORATION   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COAXIAL CABLES; DATA COMMUNICATION SYSTEMS; DIGITAL DEVICES; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY CONVERTER CIRCUITS; LSI CIRCUITS; SIGNAL RECEIVERS; TIMING CIRCUITS; TRANSMITTERS;

CLOCK AND DATA RECOVERY CIRCUIT; HIGH SPEED DATA RECOVERY CIRCUIT; MULTICHANNEL DATA TRANSMISSION; MULTICHANNEL TRANSMITTER; SELF ALIGNMENT PHASE DETECTOR; ULTRAHIGH RESOLUTION DIGITAL DISPLAY;

CMOS INTEGRATED CIRCUITS;

EID: 0034314601     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881206     Document Type: Article

References (12)

1. K. Lee, S. Kim, Y. Shin, D.-K. Jeong, G. Kim, B. Kim, V. DaCosta, and D. Lee, "A jitter-tolerant 4.5 Gb/s CMOS interconnect for digital display," in ISSCC Dig. Tech. Papers, vol. 41, Feb. 1998, pp. 310-311.
2. M. Fukaishi, K. Nakamura, M. Sato, Y. Tsutsui, S. Kishi, and M. Yotsuyanagi, "A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture." IEEE J. Solid-State Circuits, vol. 33, pp. 2139-2147, Dec. 1998.
3. C. K. Yang, R. Farjad-Rad, and M. Horowitz, "A 0.6 μm CMOS 4 Gb/s transceiver with data recovery using oversampling," in 1997 Symp. VLSI Circuits Dig., June 1997, pp. 71-72.
4. R. C. Walker, K.-C. Hsieh, T. A. Knotts, and C.-S. Yen, "A 10 Gb/s Si-bipolar TX/RX chipset for computer data transmission," in ISSCC Dig. Tech. Papers, vol. 41, Feb. 1998, pp. 302-303.
5. A. X. Widmer and P. A. Franaszek, "A dc-balanced, partitioned-block, 8 B/10 B transmission code," IBM J. Res. Develop., vol. 27, no. 5, pp. 440-451, Sept. 1983.
6. J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol 28, pp. 1273-1282, Dec. 1993.
7. S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov. 1997.
8. C. R. Hogge Jr., "A self correcting clock recovery circuit," IEEE Trans. Electron Devices. vol. ED-32, pp. 2704-2706, Dec. 1985.
9. J. D. H. Alexander, "Clock recovery from random binary signals," Electron. Lett., vol. 11, no. 22, pp. 541-542, 1975.
10. M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer, and N. Menoux, "Clock/data recovery PLL using half-frequency clock," IEEE J. Solid-State Circuits, vol. 32, pp. 1156-1159, July 1997.
11. A. Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625 Gbps transceiver with 2.r-oversampling and transmit signal pre-emphasis," in ISSCC Dig. Tech. Papers, vol. 40, Feb. 1997, pp. 238-239.
12. M. E. Lee, W. Dally, and P. Chiang, "A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation," in ISSCC Dig. Tech. Papers, vol. 43, Feb. 2000, pp. 252-253.