3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2000, Pages

  Foley, David J ^a   Flynn, Michael P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; TIMING CIRCUITS;

CLOCK SYNTHESIZERS; DELAY LOCKED LOOPS; SELF CORRECTING CIRCUITS;

DELAY CIRCUITS;

EID: 0033684559     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856308     Document Type: Conference Paper

References (7)