A novel delay-locked loop based CMOS clock multiplier

IEEE Transactions on Consumer Electronics

Volumn 44, Issue 4, 1998, Pages 1319-1322

  Birru, Dagnachew ^a,b  

^a IEEE   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS;

DELAY LOCKED LOOP (DLL); ON-CHIP CLOCK-RATE MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0032203466     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.735832     Document Type: Article

References (7)

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