A 0.6-2.5-GBaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 12, 2001, Pages 1974-1983

  Moon, Yongsam ^a,b   Jeong, Deog Kyoon ^a,b   Ahn, Gijung ^a,c  

^a IEEE   (South Korea)

^b Seoul National University   (South Korea)

^c Silicon Image Inc   (United States)

Author keywords

Clock and data recovery; Dead zone phase detection; Folded starved inverter; Serial link; Tracked 3 oversampling; Wide range multiphase delay locked loop

Indexed keywords

CLOCK AND DATA RECOVERY; DEAD-ZONE PHASE DETECTION; DELAY LOCKED LOOP; SHIELDED TWISTED PAIR CABLE;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; INTERSYMBOL INTERFERENCE; JITTER; PHASE MEASUREMENT; SIGNAL PROCESSING; TELECOMMUNICATION CABLES; VARIABLE FREQUENCY OSCILLATORS;

TRANSCEIVERS;

EID: 0035690763     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.972148     Document Type: Article

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