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Volumn 32, Issue 11, 1997, Pages 1728-1732

A 256-Mb SDRAM using a register-controlled digital DLL

Author keywords

Access control; Cylindrical capacitor; Delay locked loops; High speed devices; Sense amplifier; Synchronous DRAM

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS;

EID: 0031275108     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641693     Document Type: Article
Times cited : (47)

References (3)
  • 1
    • 0030083363 scopus 로고    scopus 로고
    • A 2.5ns clock access 25OMHz 256Mb SDRAM with a synchronous mirror delay
    • Feb.
    • T. Saeki et al., "A 2.5ns clock access 25OMHz 256Mb SDRAM with a synchronous mirror delay," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 374-375.
    • (1996) ISSCC Dig. Tech. Papers , pp. 374-375
    • Saeki, T.1
  • 2
    • 0024610684 scopus 로고
    • Twisted bit-line architectures for multi-megabit DRAM's
    • Feb.
    • H. Hidaka et al, "Twisted bit-line architectures for multi-megabit DRAM's," IEEE J. Solid-State Circuits, vol. 24, pp. 21-27, Feb. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 21-27
    • Hidaka, H.1
  • 3
    • 0030168989 scopus 로고    scopus 로고
    • Digital delay locked loop and design technique for high-speed synchronous interface
    • June
    • Y. Okajima et al., "Digital delay locked loop and design technique for high-speed synchronous interface," IEICE Trans. Electron., vol. E79-C, no. 6, pp. 798-807, June 1996.
    • (1996) IEICE Trans. Electron. , vol.E79-C , Issue.6 , pp. 798-807
    • Okajima, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.