A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 10, 2001, Pages 1498-1505

  Chen, Wei Hung ^b   Dehng, Guang Kaai ^a,b   Chen, Jong Woei ^a,b   Liu, Shen Iuan ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

CMOS; Phase locked loops; Pulsewidth modulation

Indexed keywords

PULSE DENSITY MODULATION (PDM);

DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; PHASE LOCKED LOOPS; PRINTED CIRCUIT BOARDS; PULSE WIDTH MODULATION; SIGNAL ENCODING; VARIABLE FREQUENCY OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 0035473399     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.953478     Document Type: Article

References (9)

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7. Low-jitter process-independent DLL and PLL based on self-biased techniques
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