A delay locked loop circuit with mixed-mode tuning

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 347-350

  Song, Yeo San ^a   Kang, Jin Ku ^a  

^a Inha University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 1542705756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824100     Document Type: Conference Paper

References (7)

1. M. Johnson and E. Hudson, "A variable delay line PLL for CPU coprocessor synchronization, " IEEE J. Solid-State Circuits, vol. 23, Oct. 1988.
2. Atsushi Hatakeyama, Hirohiko Mochizuki, "A 256Mb SDRAM Using a Register-Controlled Digital DLL, " IEEE J. Solid-State Circuits, vol. 32, pp. 1728-1997, NOV. 1997
3. Stefanos Sidiropoulos and Mark A. Horowitz, "A Semidigital Dual Delay-Locked Loop, " IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov. 1997
4. T. Lee, et al., "A 2. 5V CMOS delay-locked loop for an 18Mbit, 500 MB/s DRAM, " IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
5. J. Maneatis and Horowitz, " Precise delay generation using coupled oscillators, " IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993
6. J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques, " IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
7. Henrik O. Johansson, "A Simple Precharged CMOS Phase Frequency Detector, " IEEE J. Solid-State Circuits, vol. 33, pp. 295-299, FEB. 1998