A 600-MHz 54 × 54-bit multiplier with rectangular-styled Wallace tree

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 2, 2001, Pages 249-257

  Itoh, N ^a   Naemura, Y ^a   Makino, H ^a   Nakase, Y ^a   Yoshihara, T ^a   Horiba, Y ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

CMOS digital integrated circuits; Multiplication; Multiplying circuits; Redundant binary; Wallace tree

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PROBLEM SOLVING; TIMING CIRCUITS; TREES (MATHEMATICS);

RECTANGULAR-STYLED WALLACE TREES;

MULTIPLYING CIRCUITS;

EID: 0035247682     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.902765     Document Type: Article

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