High performance low power array multiplier using temporal tiling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 1, 1999, Pages 121-124

  Mahant Shetti, Shivaling S ^b   Balsara, Poras T ^a,c   Lemonds, Carl ^a,b  

^a IEEE

^b TEXAS INSTRUMENTS   (United States)

^c The University of Texas at Dallas   (United States)

Author keywords

Array multiplier; Booth encoding; Low power; Temporal tiling

Indexed keywords

ADDERS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; LOGIC DESIGN;

TEMPORAL TILING;

MULTIPLYING CIRCUITS;

EID: 0033098719     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.748208     Document Type: Article

References (5)

1. J. Leijten, J. van Meerbergen, and J. Jess, "Analysis and reduction of glitches in synchronous networks," in European Design Test Conf., 1995, pp. 398-403.
2. C. Lemonds and S. S. Mahant-Shetti, "A low power 16 by 16 multiplier using transition reduction circuitry," in Int. Workshop Low Power Design, 1994, pp. 139-140.
3. U. Ko, P. T. Balsara, and W. Lee, "A self-timed method to minimize spurious transitions in low power CMOS circuits," in Symp. Low Power Electron., 1994, pp. 62-63.
4. T. Sakuta, W. Lee, and P. T. Balsara, "Delay balanced multipliers for low power/low voltage DSP core," in Symp. Low Power Electron., 1995, pp. 36-37.
5. C. P. Lerouge, P. Girard, and J. Colardelle, "A fast 16-bit NMOS parallel multiplier," IEEE J. Solid-State Circuits, vol. SC-19, pp. 338-342, Mar. 1984.