Design and implementation of a 16 by 16 low-power two's complement multiplier

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages

  Goldovsky, Alexander ^a   Patel, Bimal ^a   Schulte, Michael ^a   Kolagotla, Ravi ^a   Srinivas, Hosahalli ^a   Burns, Geoffrey ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; ENCODING (SYMBOLS); VECTORS;

BOOTH ENCODERS; ERCEGOVAC-LANG CONVERTERS;

MULTIPLYING CIRCUITS;

EID: 18544406869     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857435     Document Type: Conference Paper

References (21)