Physical synthesis for ASIC datapath circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages 365-368

  Ye, Terry Tao ^a   Chaudhuri, Samit ^a   Huang, Felix ^a   Savoj, Hamid ^b   De Micheli, Giovanni ^b  

^a MAGMA DESIGN AUTOMATION   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA COMMUNICATION EQUIPMENT; DATA COMMUNICATION SYSTEMS; INTEGRATING CIRCUITS;

DATAPATH CIRCUITS; DATAPATH MODULES; PHYSICAL SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036287031     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010236     Document Type: Article

References (15)

1. Closing the gap between ASIC and custom: An ASIC perspective
2. The role of custom design in ASIC chips
3. Data path implementation: Bit-slice structure versus standard cells
4. Analytical approach to custom datapath design
5. AKORD: Transistor level and mixed transistor/gate level placement tool for digital data paths
6. A timing-driven data path layout synthesis with integer programming
7. Multistack optimization for data-path chip layout
8. A data path layout assembler for high performance DSP circuits
9. Layout synthesis for data-path designs
10. Data path layout optimization using genetic algorithm and simulated annealing
11. A high density data path layout generation method under path delay constraints
12. Data path placement with regularity
13. Linear ordering and application to placement
14. Relaxation and clustering in a local search framework: Application to linear placement
15. Quadratic placement revisited