Asynchronous array multiplier with an asymmetric parallel array structure

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 202-212

  Park, Chan Ho ^a   Choi, Byung Soo ^a   Lee, Dong Ik ^a   Choi, Hon Yong ^b  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b Chungbuk National University   (South Korea)

Author keywords

Clocks; Computational modeling; Concurrent computing; Delay; Digital signal processing; Encoding; Energy consumption; Logic arrays; Microprocessors; Tree data structures

Indexed keywords

CLOCKS; CONCURRENCY CONTROL; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; SIGNAL PROCESSING; TREES (MATHEMATICS);

COMPUTATIONAL MODEL; CONCURRENT COMPUTING; DELAY; LOGIC ARRAYS; TREE DATA STRUCTURES;

COMPUTATION THEORY;

EID: 0002212286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915561     Document Type: Conference Paper

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