High-speed booth encoded parallel multiplier design

IEEE Transactions on Computers

Volumn 49, Issue 7, 2000, Pages 692-701

  Yeh, Wen Chang ^b   Jen, Chein Wei ^a,b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Booth encoding; Final adder; Multiple level conditional sum adder, and parallel multiplier

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER SIMULATION; ENCODING (SYMBOLS); LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; PARALLEL PROCESSING SYSTEMS;

BOOTH ENCODING; FINAL ADDER; MULTIPLE LEVEL CONDITIONAL SUM ADDER; PARALLEL MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 0034215897     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.863039     Document Type: Article

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