Failure analysis of open faults by using detecting/un-detecting information on tests

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 222-227

  Sato, Yuichi ^a   Takahashi, Hiroshi ^a   Higami, Yoshinobu ^a   Takamatsu, Yuzo ^a  

^a EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; BUILT-IN SELF TEST; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; DEFECTS; FAILURE ANALYSIS; LOGIC CIRCUITS; VLSI CIRCUITS;

FAULT SIMULATION; LOGIC DESIGNS; METAL INTERCONNECTS; STUCK-AT-FAULTS;

ELECTRIC FAULT CURRENTS;

EID: 13244271272     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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