-
2
-
-
0030409794
-
Modelling the unmodellable: Algorithmic fault diagnosis
-
R.C. Aitken, "Modelling the Unmodellable: Algorithmic Fault Diagnosis", in Proc. of Int'l Test Conference, 1996, pp. 931-940.
-
Proc. of Int'l Test Conference, 1996
, pp. 931-940
-
-
Aitken, R.C.1
-
3
-
-
0032643282
-
Multiple error diagnosis based on xlists
-
B. Boppana, R. Mukherjee, J. Jain, and M. Fujita, "Multiple Error Diagnosis Based on Xlists," in Proc. of Design Automation Conf., June 1999, pp. 100-110.
-
Proc. of Design Automation Conf., June 1999
, pp. 100-110
-
-
Boppana, B.1
Mukherjee, R.2
Jain, J.3
Fujita, M.4
-
4
-
-
0003934798
-
SIS: A system for sequential circuit synthesis
-
University of California, Berkeley, Tech. Report
-
R.K. Brayton et al., "SIS: A System for Sequential Circuit Synthesis," University of California, Berkeley, Tech. Report, 1992.
-
(1992)
-
-
Brayton, R.K.1
-
5
-
-
0022769976
-
Graph-based algorithms for Boolean function manipulation
-
Aug.
-
R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.
-
(1986)
IEEE Trans. on Computers
, vol.35
, Issue.8
, pp. 677-691
-
-
Bryant, R.E.1
-
6
-
-
0027149630
-
Diagnosis and correction of logic design errors in digital circuits
-
P.Y. Chung, Y.M. Wang, and I.N. Hajj, "Diagnosis and Correction of Logic Design Errors in Digital Circuits," in Proc. of Design Automation Conf., June 1993, pp. 503-508.
-
Proc. of Design Automation Conf., June 1993
, pp. 503-508
-
-
Chung, P.Y.1
Wang, Y.M.2
Hajj, I.N.3
-
8
-
-
0031380361
-
Errortracer: A fault simulation based approach to design error diagnosis
-
S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and D.-T. Cheng, "ErrorTracer: A Fault Simulation Based Approach to Design Error Diagnosis," in Proc. of Int'l Test Conf., Nov. 1997, pp. 974-981.
-
Proc. of Int'l Test Conf., Nov. 1997
, pp. 974-981
-
-
Huang, S.-Y.1
Cheng, K.-T.2
Chen, K.-C.3
Cheng, D.-T.4
-
9
-
-
0029309287
-
Yield-oriented computer-aided defect diagnosis
-
May
-
J.B. Khare, W. Maly, S. Griep, and D. Schmitt-Landsiedel, "Yield-Oriented Computer-Aided Defect Diagnosis," IEEE Transactions on Semiconductor Manufacturing, vol. 8, no. 2, pp. 195-206, May 1995.
-
(1995)
IEEE Transactions on Semiconductor Manufacturing
, vol.8
, Issue.2
, pp. 195-206
-
-
Khare, J.B.1
Maly, W.2
Griep, S.3
Schmitt-Landsiedel, D.4
-
10
-
-
0028592997
-
Error diagnosis for transistor-level verification
-
A. Kuehlmann, D.I. Cheng, A. Srinivasan, and D.P. Lapotin, "Error Diagnosis for Transistor-Level Verification," in Proc. of Design Automation Conf., June 1994, pp. 218-223.
-
Proc. of Design Automation Conf., June 1994
, pp. 218-223
-
-
Kuehlmann, A.1
Cheng, D.I.2
Srinivasan, A.3
Lapotin, D.P.4
-
11
-
-
0030383964
-
Beyond the Byzantine generals: Unexpected behavior and bridging fault diagnosis
-
D.B. Lavo, T. Larabee, and B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis," in Proc. of Int'l Test Conference, 1996, pp. 611-619.
-
Proc. of Int'l Test Conference, 1996
, pp. 611-619
-
-
Lavo, D.B.1
Larabee, T.2
Chess, B.3
-
15
-
-
0001448647
-
Bridging fault diagnosis using stuck-at fault simulation
-
April
-
J. Wu and E.M. Rudnick, "Bridging Fault Diagnosis Using Stuck-at Fault Simulation," IEEE Trans. on Computer-Aided Design, vol. 19, no. 4, pp. 489-495, April 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design
, vol.19
, Issue.4
, pp. 489-495
-
-
Wu, J.1
Rudnick, E.M.2
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