Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 261-274

  Mai, Ken ^a   Ho, Ron ^c   Alon, Elad ^b   Liu, Dean ^d   Kim, Younggon ^b   Patil, Dinesh ^b   Horowitz, Mark A ^b  

^a Stanford University   (United States)

^b STANFORD UNIVERSITY   (United States)

^c SUN MICROSYSTEMS   (United States)

^d Aeluros Inc   (United States)

Author keywords

Memory; Reconfigurable logic; SRAM

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; LOGIC DEVICES; METADATA; TIMING CIRCUITS; WAVEFORM ANALYSIS;

DATA ARRAYS; RECONFIGURABLE LOGIC; RECONFIGURABLE MEMORY; ROOM TEMPERATURE;

STATIC RANDOM ACCESS STORAGE;

EID: 11944272652     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.837992     Document Type: Conference Paper

References (33)

1. P. Silverman, "Who can afford advanced lithography?," in Microlithography World, Nov. 2003.
2. R. Merritt, "Gurus urge IC design overhaul," EE Times, Sep. 2, 2003.
3. N. Zhang and R. Brodersen. (2002) The cost of flexibility in systems on a chip design for signal processing applications. [Online]. Available: http://bwrc.eecs.berkeley.edu/Classes/EE225C/Papers/arch_design.doc
4. D. Parlour, "The reality and promise of reconfigurable computing in digital signal processing," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tutorial, San Francisco, CA, Feb. 2004.
5. R. Sites, "It's the memory, stupid!," Microprocessor Rep., pp. 19-20, Aug. 5, 1996.
6. D. Albonesi, "Selective cache ways: On-demand cache resource allocation," presented at the Int. Symp. Microarchitecture, Haifa, Israel, Nov. 1999.
7. P. Ranganathan et al., "Reconfigurable caches and their application to media processing," in Proc. Int. Symp. Computer Architecture, Vancouver, BC, Canada, Jun. 2000, pp. 214-224.
8. C. Zhang, F. Vahid, and W. Najjar et al., "A highly configurable cache architecture for embedded systems," in Proc. Int. Symp. Computer Architecture, San Diego, CA, Jun. 2003.
9. "TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B)," Texas Instruments, Inc., Jun. 2004. TI Literature Number SPRU609B. [Online.] Available: http://www-s.ti.com/sc/psheets/spru609b/spru609b. pdf.
10. B. Ackland et al., "A single chip, 1.6-billion, 16-b MAC/s multiprocessor DSP," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 412-424, Mar. 2000.
11. "Using the Virtex Block SelectRAM+ Features," Xilinx Inc., Dec. 18, 2000. Application Note XAPP130. [Online.] Available: http://www.xilinx.com/ bvdocs/appnotes/xapp130.pdf.
12. "TriMatrix Embedded Memory Blocks in Stratix II Devices, Stratix II Device Handbook, vol. 2, ch. 2," Altera Inc., Jul. 2004. Document Number SII5V2-1.3. [Online.] Available: http://www.altera.com/literature/hb/stx2/ stratix2_handbook.pdf.
13. F. Heile et al., "Programmable memory blocks supporting content-addressable memory," in Proc. 8th Int. ACM Symp. Field Programmable Gate Arrays, 2000, pp. 13-21.
14. S. Guccione et al., "A reconfigurable content addressable memory," in Proc. 15th Int. Parallel and Distributed Processing Workshops (IPDPS), May 2000, pp. 882-889.
15. B. Amrutur and M. Horowitz, "Speed and power scaling of SRAMs," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 175-185, Feb. 2000.
16. J. Hennessy, D. Goldberg, and D. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufmann, 1996.
17. K. Mai et al., "Smart memories: A modular reconfigurable architecture," in Proc. Int. Symp. Computer Architecture, Jun. 2000, pp. 161-71.
18. M. Horowitz and W. Dally, "How scaling will change processor architecture," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 132-133.
19. D. Sager et al., "A 0.18 μm CMOS IA32 microprocessor with a 4 GHz integer execution unit," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 324-325, 461.
20. M. Matson et al., "Circuit implementation of a 600 MHz superscalar RISC microprocessor," in Proc. Int. Conf. Computer Design, Oct. 1998, pp. 104-110.
21. S. Hsu et al., "A 4.5-GHz 130-nm 32-KB LO cache with a leakage-tolerant self reverse-bias bitline scheme," IEEE J. Solid-State Circuits, vol. 38, pp. 755-761, May 2003.
22. T. Chappell et al., "A 2-ns cycle, 3.8-ns access 512 kb CMOS ECL SRAM with a fully pipelined architecture," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1577-1585, Nov. 1991.
23. B. Amrutur and M. A. Horowitz, "Fast low-power decoders for RAMs," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1506-1515, Oct. 2001.
24. H. Nambu et al., "A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1998, pp. 360-361, 464.
25. T CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1421-1432, Nov. 2002.
26. K. Sakai et al., "A 15 ns 1-Mbit CMOS SRAM," IEEE J. Solid-State Circuits, vol. 23, no. 10, pp. 1067-1072, Oct. 1988.
27. M. Matsumiya et al., "A 15 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture," IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1497-1503, Nov. 1992.
28. K. Mai et al., "Low-power SRAM design using half-swing pulse-mode techniques," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1659-1671, Nov. 1998.
29. B. Nikolic et al., "Sense amplifier-based flip-flop," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999, pp. 282-283.
30. B. Amrutur and M. A. Horowitz, "A replica technique for wordline and sense control in low-power SRAMs," IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1208-1219, Aug. 1998.
31. K. Mai et al., "Architecture and circuit techniques for a reconfigurable memory block," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, p. 500.
32. R. Ho, K. Mai, and M. A. Horowitz, "Efficient on-chip global interconnects," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 271-274.
33. R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mon, and M. Horowitz, "Applications of on-chip samplers for test and measurement of integrated circuits," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1998, pp. 138-139.