Architecture and circuit techniques for a reconfigurable memory block

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Mai, Ken ^a   Ho, Ron ^a   Alon, Elad ^a   Liu, Dean ^a   Kim, Younggon ^a   Patil, Dinesh ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODERS; MEMORY BLOCKS; MEMORY STRUCTURES; MEMORY SYSTEMS;

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED MANUFACTURING; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC; METADATA; MICROPROCESSOR CHIPS;

STATIC RANDOM ACCESS STORAGE;

EID: 2442646843     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Mai et al., "Smart Memories: a Modular, Reconfigurable Architecture," Intl. Symp. on Comp. Arch., pp. 161-171, 2000.
2. B. Amrutur et al., "Speed and Power Scaling of SRAM's," IEEE J. Solid-State Circuits, vol. 25, pp. 175-185, Feb. 2000.
3. T. Chappell et al., "A2-ns Cycle, 3.8ns Access 512kb CMOS ECL SRAM with a Fully Pipelined Architecture," IEEE J. Solid-State Circuits, pp. 50-51, Nov. 1991.
4. J. Hennessy and D. Patterson, "Computer Architecture a Quantitative Approach," 2nd Ed., 1996.
5. R. Ho et al., "Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits," Symp. on VLSI Circuits Dig., pp. 138-139, Jun. 1998.