Inherently linear capacitor error-averaging techniques for pipelined a/d conversion

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 3, 2000, Pages 229-232

  Chiu, Yun ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Active capacitor error averaging; Average residue voltage; Complementary residue pair; DNL; Effective number of bits; INL; Passive capacitor error averaging; Pipelined A D conversion; SNDR

Indexed keywords

COMPUTER SIMULATION; INTEGRAL EQUATIONS; LINEAR NETWORK ANALYSIS; PIPELINE PROCESSING SYSTEMS;

INTEGRAL NONLINEARITY (INL);

ANALOG TO DIGITAL CONVERSION;

EID: 0033890089     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.826750     Document Type: Article

References (11)

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