A timing-constrained algorithm for simultaneous global routing of multiple nets

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 99-103

  Hu, Jiang ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; TIMING CIRCUITS; TRAFFIC CONGESTION; CONSTRAINT THEORY; DELAY CIRCUITS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; OPTIMIZATION; TRANSMISSION LINE THEORY; VLSI CIRCUITS;

BENCHMARK CIRCUIT; CONGESTION REDUCTION; GLOBAL ROUTING; NEW APPROACHES; ROUTING TOPOLOGY; TIMING CONSTRAINED ALGORITHM; TIMING CONSTRAINTS; VLSI INTERCONNECTS;

COMPUTER AIDED DESIGN;

DELAY MODEL; GLOBAL ROUTING; ROUTING TOPOLOGY; SINGLE NET ROUTING ALGORITHM; TIMING CONSTRAINED ALGORITHM;

EID: 0034478158     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896457     Document Type: Conference Paper

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