A highly efficient domain-programmable parallel architecture for iterative LDPCC decoding

Proceedings - International Conference on Information Technology: Coding and Computing, ITCC 2001

Volumn , Issue , 2001, Pages 569-577

  Al Rawi, G ^a   Cioffi, J ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; DECODING; DISTRIBUTED COMPUTER SYSTEMS; ITERATIVE DECODING; ITERATIVE METHODS; MEMORY ARCHITECTURE; MESSAGE PASSING; NETWORK ARCHITECTURE;

COMPUTATIONAL RESOURCES; DEADLOCK AVOIDANCE; ITERATIVE PROBABILISTIC DECODING; PROGRAMMABLE PARALLEL ARCHITECTURES; PROPOSED ARCHITECTURES; SEQUENTIAL IMPLEMENTATION; STATE MANAGEMENT; STORE AND FORWARD;

PARALLEL ARCHITECTURES;

EID: 0001955815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITCC.2001.918858     Document Type: Conference Paper

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